Beteiligt an Projekt/Förderung PSIMU Förderung Rauschmessungen von 22FDX-Strukturen (inkl. Komparatoren) mit und ohne hochohmigen FDSOI Substraten Förderung WINFDSOI Förderung WINFDSOI Förderung
Publikation (Autor/in) (Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits Wissenschaftlicher Artikel A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs Tagungsband A wired-AND transistor: Polarity controllable FET with multiple inputs Konferenz-Paper Analyse und Optimierung von verspannten Schichten auf CMOS–Transistoren Konferenz-Paper Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform Konferenz-Paper Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits Tagungsband Enabling Energy Efficiency and Polarity-Control in Germanium Nanowire Transistors by Individually Gated Nano-Junctions Wissenschaftlicher Artikel Entwicklung von energieeffizienten Hochleistungstransistoren Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors Wissenschaftlicher Artikel Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation Wissenschaftlicher Artikel Improvement of low-frequency noise behavior with chloridic precursor materials at ALD process Wissenschaftlicher Artikel In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs Konferenz-Paper Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels Konferenz-Paper Scaling Aspects of Nanowire Schottky Junction based Reconfigurable Field Effect Transistors Tagungsband Simulation and Optimization of Tri-Gates in a 22nm Hybrid Tri-Gate/Planar Process Konferenz-Paper Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors Tagungsband Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond Tagungsband Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors Wissenschaftlicher Artikel Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process Tagungsband Suppression of the corner effects in a 22 nm hybrid tri-gate/planar process Konferenz-Paper Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents Wissenschaftlicher Artikel Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors Wissenschaftlicher Artikel Vertically Integrated Reconfigurable Nanowire Arrays Wissenschaftlicher Artikel A Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation Wissenschaftlicher Artikel High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits (Invited) Konferenz-Paper Optimization of Stressor Overlayer Parameters for MOSFET's in "Cool Silicon" – Technologies Konferenz-Paper Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits Tagungsband Strain Analysis for Reconfigurable Silicon Nanowire Devices Konferenz-Paper Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized? Wissenschaftlicher Artikel The RFET-a reconfigurable nanowire transistor and its application to novel electronic circuits and systems Wissenschaftlicher Artikel
Dissertation Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie Abschlussarbeit
ausgewählte Veröffentlichungen konferenz-paper A wired-AND transistor: Polarity controllable FET with multiple inputs 2018 In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs 2017 Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform 2016 Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels 2012 Simulation and Optimization of Tri-Gates in a 22nm Hybrid Tri-Gate/Planar Process 2011 Suppression of the corner effects in a 22 nm hybrid tri-gate/planar process 2011 tagungsband Scaling Aspects of Nanowire Schottky Junction based Reconfigurable Field Effect Transistors 2019 A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs 2018 Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors 2016 Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits 2015 Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond 2012 Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process 2011 wissenschaftlicher artikel Improvement of low-frequency noise behavior with chloridic precursor materials at ALD process. Memories - Materials, Devices, Circuits and Systems. 2024 Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation. IEEE transactions on nanotechnology. 21. 2022 Vertically Integrated Reconfigurable Nanowire Arrays. IEEE electron device letters. 39. 2018 Enabling Energy Efficiency and Polarity-Control in Germanium Nanowire Transistors by Individually Gated Nano-Junctions 2017 Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents. IEEE transactions on nanotechnology. 16. 2017 Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors. Solid-state electronics. 128. 2017 (Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits. Meeting abstracts (Electrochemical Society). MA2016-02. 2016 Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors. IEEE transactions on nanotechnology. 14. 2015 Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors. IEEE electron device letters. 36. 2015